A 0.5-5-GHz Wide-Range Multiphase DLL With a Calibrated Charge Pump

نویسندگان

  • Chi-Nan Chuang
  • Shen-Iuan Liu
چکیده

A 0.5–5 GHz wide-range multiphase delay-locked loop (MDLL) with a calibrated charge pump is presented. A multiperiod-locked technique is used to enhance the input frequency range of a MDLL and avoid the harmonic-locked problem. The charge pump current is also calibrated to reduce the static phase error. This MDLL has been fabricated in 0.13m CMOS process. The measured root-mean-square and peak-to-peak jitters are 1.06 and 8 ps at 5 GHz, respectively. The power dissipation at 5 GHz is 36 mW for a supply voltage of 1.2 V.

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

A Self Calibrated Based Clock Generator for DLL

In this paper, a Delay-Locked Loop (DLL) based clock generator is designed which can be used mainly for dynamic frequency scaling. This DLL-based clock generator is found to have low-jitter and can provide the system clock with frequencies in the range of 0.5 to 8 times of reference clock, depending on the workload of the EISC processor. This proposed analog self-calibration method and a phase ...

متن کامل

Design of a Sub-Picosecond Jitter with Adjustable-Range CMOS Delay-Locked Loop for High-Speed and Low-Power Applications

A Delay-Locked Loop (DLL) with a modified charge pump circuit is proposed for generating high-resolution linear delay steps with sub-picosecond jitter performance and adjustable delay range. The small-signal model of the modified charge pump circuit is analyzed to bring forth the relationship between the DLL's internal control voltage and output time delay. Circuit post-layout simulation shows ...

متن کامل

Low Settling Time All Digital DLL For VHF Application

Settling time is one of the most important parameter in design of DLLs. In this paper we propose a new high speed with low settling time Delay Locked Loop (DLL) in which a digital signal processor (DSP) is used instead of using phase-frequency detector, charge pump and loop filter in conventional DLL. To have better settling time, PRP conjugate gradient algorithm is used to optimize delay of ea...

متن کامل

طراحی ضرب کننده فرکانسی بر اساس حلقه قفل شده تاخیر دیجیتالی و با سرعت بالا

Lock and settling times are two parameters which are of high importance in design of DLL-based frequency multipliers. A new architecture for DLL-based frequency multipliers in digital domain is designed in this paper. In the proposed architecture instead of using charge pump, phase frequency detector and loop filter a digital signal processor is used. Gradient algorithm is used in the proposed ...

متن کامل

Design of Self Calibrated DLL Based Clock Generator Using Modified GDI Technique

This paper describes a low-jitter delay-locked loop (DLL)-based clock generator for dynamic frequency scaling in the extendable instruction set computing (EISC) processor. The DLL-based clock generator provides the system clock with frequencies of the reference clock, according to the workload of the EISC processor. The proposed self-calibration method and a phase detector with an auxiliary cha...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

عنوان ژورنال:
  • IEEE Trans. on Circuits and Systems

دوره 54-II  شماره 

صفحات  -

تاریخ انتشار 2007